DesignCon

As data rates continue to surge, the debate over the viability of copper interconnects intensifies. For over 25 years, the industry has grappled with predictions of copper's demise, yet it remains a cornerstone of connectivity. With the advent of 448Gbps data rates, we must ask: are these warnings merely alarmist, or have we truly reached the fundamental limits of copper interconnect technology? This panel brings together a distinguished group of experts from across the industry, including package vendors, interconnect specialists, system designers, and test and validation professionals. Together, they will explore the possibilities and limitations of copper interconnects, identify the challenges that must be addressed, and discuss strategies to meet system budget constraints. Join us for an insightful discussion on the future of copper in high-speed data transmission.

As AI workloads grow exponentially, traditional interconnects, designed for scale-out or proprietary setups, are struggling to keep pace with the demands for bandwidth, latency, and scalability in next-generation AI systems. UALink is an open, memory-semantic fabric purpose-built for scale-up architectures, enabling direct memory access and atomic operations across up to 1,024 GPUs. With 200 Gbps per lane and sub-microsecond latency, it supports tightly coupled AI workloads. The 200G 1.0 spec, released in April 2025, sets a vendor-neutral foundation, but deployment requires broad ecosystem collaboration across hardware, software, and systems. In this session, Astera Labs, a founding Board Member of the UALink Consortium, will join with other panelists to discuss the practical challenges and breakthrough solutions behind deploying UALink at rack scale. Attendees will gain insights into memory semantics, protocol optimization, power and cost efficiencies, and the multi-vendor ecosystem driving this industry-wide transformation. With over 100 member companies fueling adoption, UALink is set to redefine how AI infrastructure scales-up, and this panel session will offer a front-row seat to that evolution. Read More

As AI rapidly transforms the EDA landscape, disciplines like software, verification, Physical Design, and system architecture have seen increasing support from machine learning tools. However, AI adop...

Now in its 5th year, Test on Wheels returns with a sharper technical focus and timely insights into the evolving world of automotive compliance testing. This year’s panel takes a deep dive into the...

High speed oscilloscopes have been the primary tool for analyzing data dependent jitter or DDJ, an important source of distortion on high-speed digital signals such as PCIe. Increasing symbol rates co...

Self-generated EMI on wireless devices can cause reduced receiver sensitivity. Energy sources such as digital bus noise and DC-DC converters are largely to blame. This presentation describes ten ways ...

Current data rates for various high-speed signaling protocols necessitate high-frequency material loss characterization to 67 GHz. Further, to facilitate fast and easy characterization, a probing solution is ideal. In this work, a solution has been developed for insertion loss characterization on printed circuit materials up to 67 GHz using a pair of mechanically robust GSSG probes. De-embedding of the probes is done using the Delta-L method detailed in IPC 2.5.5.14. To achieve an upper frequency of 67 GHz requires careful design of the probe footprint and via transition to a stripline layer. In this presentation, the design procedure and tight tolerances will be discussed and demonstrated through several test vehicles. S-parameter measurements, and de-embedding requirements for a design that achieves 67 GHz will be shown and discussed. The de-embedding and IL extraction tool will be demonstrated, and insertion-loss from measurements will be shown and discussed.  An approach for in-circuit-board characterization has also been developed and quantified from this work.

High-speed data transmission is crucial for modern digital infrastructure, supporting applications from cloud computing to autonomous vehicles. As data demands surge, driven by advancements in AI, machine learning, and big data analytics, the need for higher data rates becomes urgent. This paper explores the challenges in transitioning from 224 Gbps to 448 Gbps for scale-up and scale-out applications. The paper provides an overview of optical technologies necessary for 448 Gbps transmission, examining advancements required in modulation techniques, signal processing, and materials science. It discusses strategies to overcome challenges related to signal integrity, power consumption, and thermal management. Furthermore, the paper highlights the importance of collaboration between industry stakeholders, including hardware manufacturers, network operators, and standards organizations, to ensure seamless integration and deployment of these technologies. By addressing these challenges, the industry can pave the way for more robust and efficient digital infrastructure, capable of meeting the growing demands of data-intensive applications.   Read More

Integrated circuit (IC) immunity failures in automotive and industrial systems are often the result of unintended noise coupling from complex harnesses and passive components that propagate disturbances directly to IC pins. Despite growing concerns in EMC design, the noise susceptibility of ICs is rarely considered during the early phases of IC or system design. This gap largely stems from the absence of accurate system-level estimation and impact analysis methods that capture how injected noise translates into IC-level disturbances. The challenge arises due to the complex nature of the system, which includes wire harnesses, non-linear components such as current-injecting clamps, printed circuit boards (PCBs), active and passive circuits, and noise injection paths. In our previous work, we demonstrated that these challenges can be addressed using a hybrid modeling approach—combining full-wave electromagnetic simulations based on the Method of Moments (MoM) with network-based system modeling techniques. Key elements such as injection clamps, termination networks, and passive components are modeled with equivalent circuit representations, while active circuits are characterized using their impedance profiles and IC Immunity Models (ICIM) derived from Direct Power Injection (DPI) measurements. Read More

Traditionally, a high-bandwidth memory (HBM) interposer design requires exhaustive manual electromagnetic (EM) simulations to ensure the required signal integrity across the channel. This process requires balancing numerous geometric and process parameters through trial-and-error, making it both time-consuming and cost-intensive, and significantly limiting the exploration of design space. To address these challenges, we propose a robust, machine learning (ML) based design flow that efficiently combines pre-layout optimizations and post-layout high-volume manufacturing (HVM) verification. In the pre-layout stage, a neural network model is trained to predict key performance metrics from interposer geometry. Then a multi-objective genetic algorithm (NSGA-II) uses this surrogate model to efficiently explore the design space. At the post-layout design phase, a long-short term memory (LSTM)-based model is employed to predict the full-channel S-parameters at different process-voltage-temperature corners, thereby reducing the number of costly EM extractions needed for HVM corner analysis. This new workflow enables rapid identification of an optimal HBM interposer design and significantly accelerates verification across manufacturing variations without sacrificing accuracy. To validate the proposed methodology, an interposer designed using this flow was fabricated and extensively tested in the lab, showing strong correlation with simulations results.   Read More

AI accelerators consist of numerous chiplets in advanced heterogeneous packages, consume power and have hundreds of Serdes lanes. The PCBs that house these packages face numerous PDN design challenges. The highest power compute chiplet, typically situated in the package center, has its PDN barricaded by neighboring chiplets’ power vias to backside decoupling capacitors, rendering high conductive losses. High scale-up domain for AI training puts pressure on PCB miniaturization, leaving little room for capacitors and VRMs. Serdes and power are routed on many layers to ensure SI and PI, resulting in a thick PCB with high via inductance to backside decoupling capacitors. This paper proposes a novel PCB capacitor block embedding process that addresses the aforementioned challenges. 8x capacitor blocks are embedded within the PCB very close to the BGA surface, under the die shadow, using a sequential lamination process. This process supports complex and thick AI PCBs (>40L/5mm) with dual current paths above and below the capacitor block enabling low ESL for transient current from above, and low resistance DC path from below. Embedding removes the PTH vias that barricade the compute chiplet for improved lateral power delivery. For vertical power delivery, capacitor embedding enables utilization of off-the-shelf VRMs, instead of needing a custom module. This translates to space savings, faster time to market and lower assembly risks. PDN simulations with the novel PCB structure show improved transient response to support AI kernels with aggressive PDN requirements.

The rapid growth of streaming, cloud computing, and AI applications is driving the need for ever-higher data rates. While 224 Gbps PAM4 systems are currently under development, standards bodies such as IEEE and OIF are already investigating 448 Gbps solutions.  Prior work on 224 Gbps channels has shown that reliable signal recovery often requires bandwidths extending well beyond the Nyquist frequency. However, doubling the data rate to 448 Gbps also doubles the Nyquist frequency—from 56 GHz to 112 GHz—posing significant new challenges. This wide step forward will involve a significant effort towards solving two main problems. 1. Designing a channel for a smooth resonance-free response, 2. Avoiding a large decrease of the SNR making the received eye detectable at a given Symbol-Error-Rate (SER). Both aspects involve the improvement of the channel spectral efficiency while applying the best equalization architecture and, at the same time, having the capability to optimize the equalization parameters. The objective of this paper is to make a comprehensive analysis identifying the best equalizers to recover a 448 Gbps PAM4 signal on a channel whose spectrum shows a significant roll-off or resonances laying below Nyquist frequency.

In high-speed DDR links (MRDIMM) for server applications, the shrinking margins due to increased data rates and lane density have intensified crosstalk issues, necessitating improvements in signal integrity (SI). This paper addresses the critical need for accurate modeling of link impairments to ensure robust designs. Because of the increase in lane density and traffic, power supply noise (PSN) is an important aspect of link budgeting. In this work, we investigate the impact of Host and DIMM power supply noise on link performance during read and write operations. We examine the voltage (dv) and time (dt) impact of the supply noise and quantify its effect on overall link margins. Our analysis highlights the distinct contributions of the transmitter (Tx) and receiver (Rx) to voltage and timing margins, detailing a methodology for integrating PSN effects into DDR link assessments. We present results based on realistic traffic signatures for PSN profiles, comparing these findings to a model-based approach for early evaluation. This work will conclude with a complete framework for PSN inclusion and evaluation for high-speed DDR links, offering valuable insights for the design and optimization of next-generation server memory interfaces.

S-parameters are the most common format used for exchanging measurements and simulations in high-speed design.  The measurement and simulation of s-parameters assumes certain things, notably, how the port is defined.  Most simulators provide s-parameters with ports defined as the difference between a signal and reference grounds.  The implications of this are very important in interpreting these, in use in simulations, and especially with regard to cascading them.  This paper removes this mystery and provides rigorous mathematical "proofs" and details with how the engineer must properly deal with s-parameter ports.

The growing demand for scalable AI acceleration has driven a shift from monolithic SoC designs to modular chiplet-based architectures, offering greater customization, reusability, and time-to-market advantages. However, conventional chiplet systems fix the architecture early, limiting flexibility when functional requirements or vendors change. In contrast, the emerging open chiplet ecosystem enables dynamic system assembly using heterogeneous chiplets from multiple vendors and interfaces, requiring intelligent automation to ensure system-level performance and signal integrity (SI). This thesis presents a comprehensive framework for chiplet placement and routing optimization targeting AI workloads. The problem is formulated as a hierarchical Markov Decision Process (MDP), and expert trajectories are generated using a deterministic Place-to-Route (P2R) heuristic guided by an SI-aware look-up-table (LUT) model. A Graph Attention Network (GAT)–based neural agent is trained via imitation learning to mimic these expert strategies. To enhance generalization, the framework incorporates symmetricity-based data augmentation, leveraging spatial invariances in chiplet placement to expose the model to diverse valid layouts. Throughput-based reward modeling and a post-inference refinement step ensure both high performance and area efficiency. Experiments confirm 100% valid layouts, strong generalization, and superior performance over baselines—advancing practical design automation for a fully customizable chiplet ecosystem. Read More

Keysight is unveiling a patent-pending, end-to-end electrical-optical-electrical (EOE) design and simulation workflow that uniquely connects system-level Ethernet design with true photonic accuracy. By integrating Keysight ChannelSim with Keysight Photonic Designer, this solution allows Ethernet system designers to natively embed an optical block representing the photonic integrated circuit (PIC) in full detail, leveraging deep-physics-based models instead of simplified black-box abstractions. For the first time, system architects and photonic engineers can analyze the complete EOE link from electrical transmitter, through the photonic chip including layout, to the electrical receiver within a single, unified simulation environment. This tight integration provides unprecedented visibility into performance, margin, and design trade-offs early in the workflow, dramatically reducing risk, design iterations, and time-to-market for next-generation optical Ethernet systems.As data rates increase, the need to go beyond copper and extend the channel reach with managable channel loss is ever more important. This new simulation methodology allows the co-simulation of photonic components and channel simulation in one flow.

With the growing complexity of modern hardware systems and the shortening of design cycles, there is a compelling demand for more efficient and faster PDN design methodologies. Machine learning can play a pivotal role and offer capabilities that were not possible in conventional ways. This talk will introduce recent progress in machine learning applications in PDN design, including pre-layout synthesis and post-layout optimization, in a practical setting.

The growing adoption of Ethernet in artificial intelligence (AI) and high-performance computing (HPC) applications has driven the development of high-bandwidth, low-latency, and lossless interconnect technologies for beyond 1.6 TbE with 400+ Gb/s per lane High-order modulations, such as PAM4, PAM6 with 5 bits-2 consecutive senary symbols (5B2S) and high- efficiency 18 bits-7 consecutive senary symbols (18B7S) scheme, and PAM8 with DSQ32, are investigated. PAM6 and PAM8 suffer from poorer noise tolerance than PAM4, which will ask higher signal-to-noise ratio (SNR) to compensate modulation penalty. Moderate stronger FEC, such as RS(544,514) with higher FEC symbol size based on Galois field 212 and 215 or higher performance version RS(560,514) for 18B7S to reach similar line rate to RS(544,514) for 5B2S or DSQ32 is reasonable approach. Lossless and low latency are achievable by light-weight RS FEC based link level retry (LLR). We build a Monte Carlo simulation model, in which PAM4, 6, 8 coding physical link errors are generated based on an additive white gaussian noise (AWGN) channel combined with a 1-tap DFE incorporating error propagation characterized by probability factor. Capability metrics of RS(544, 514), RS(560, 514), RS(272, 258), and RS(280, 258) with link level retry (LLR), such as required signal-to-noise ratio (SNR), PAM symbol error ratio (SER), frame loss ratio (FLR), throughput loss ratio, and mean time to false packet acceptance (MTTFPA) etc., are simulated and analyzed. For future Ethernet technology and standard development in LLR scenario, one should consider the feasible FLR/FLRr objective and related relaxed requirements for the physical link, latency variation, and throughput loss to application, as well as the reliability risk of light-weight FEC. We suggest to improve 1X RS(272, 258) based solution.

The rapid growth of artificial intelligence (AI) workloads and data center demands has driven the need for ultra-high-speed interconnects supporting 400 Gb/s. Higher-order Pulse Amplitude Modulation (PAM) schemes like PAM6 offer increased spectral efficiency but are highly sensitive to impairments such as P/N skew, caused by timing mismatches in differential signals. This work develops an analytical framework to derive P/N skew for coupled transmission lines and models the impact of skew on 400G PAM6 SerDes. Frequency-dependent skew behaviors, represented by flat, cosine oscillated, damped oscillated, and Gaussian single-peak shapes, are mathematically modeled using S-parameters to capture realistic skew profiles in strongly and weakly coupled channels. Simulations quantify skew tolerances based on BER degradation. Results reveal that flat skews in weakly coupled channels (e.g., stripline) cause the most significant BER increase, while damped oscillated skews in strongly coupled systems (e.g., cables and microstrip) have a moderate impact due to frequency attenuation. Gaussian skews, caused by localized discontinuities, are least disruptive. Flat and cosine skews are the most damaging due to their sustained effects across frequency ranges. This work provides analytical insights and actionable design guidelines to address P/N skew challenges, ensuring reliable 400G interconnects for AI-driven data centers and next-generation networks. Read More

A deep reinforcement learning (DRL) approach is proposed for optimizing the package interconnection design of 3D-IC substrate considering multiple power domain (MPD) environments. While MPD in 3D-IC enables power savings by selectively activating cores tailored to power requirement, it introduces design challenges such as complex domain-to-domain noise interactions and a vast combinatorial design space. The optimization targets include package plane arrangement, package decoupling capacitor placement, and BGA assignment. To address these challenges and design objectives, a multi-agent DRL algorithm within a hierarchical reinforcement learning (HRL) framework is adopted. HRL decomposes the complex multi-stage optimization into manageable sub-tasks enabling more efficient learning, localized reward assignment, and scalable decision-making across interdependent design constrains. The proposed method achieves SSN suppression while satisfying electromigration condition of BGA and enabling low partial PDN impedance of BGA. The proposed method demonstrates generalization performance with variously displaced placement seed map and different types of switching current profiles. The optimality performance of the proposed method is validated by comparing it with conventional optimization algorithm and flat DRL approaches. The proposed method outperforms the other optimization methods in terms of computation time and optimality performance across various tests with different seed map and switching current profiles.

Simultaneous Bi-Directional (SBD) signaling is an innovative scheme for die-to-die chiplet interconnects aiming at solving one of the biggest challenges that our industry faces: the ability to process massive amounts of data with the highest efficiency and the lowest power consumption. This paper presents the first industry attempt at developing a methodology to use IBIS-AMI models for analyzing SBD links. Since IBIS-AMI models only support communication in one direction, a simple yet effective approach is presented that captures the important aspects of SBD operation while utilizing unidirectional models. Various operating scenarios are studied, and the models are shown to accurately predict the behavior of the system. Finally, the models are compared against real silicon, proving the accuracy of the models as well as validating our approach to modeling SBD links.

The rapid growth in Data Centers, AI, and supercomputing demands significantly faster edge rates at the package and PCB levels, necessitating superior power delivery network (PDN) solutions. While traditional VRMs and bulk capacitors dominate at lower frequencies, the impact and effectiveness of embedded capacitors in high-current PDNs remain critical for achieving high performance. This paper explores various embedded capacitor technologies and their layout considerations within PCB and package stackups. Through detailed simulation and measurement, we analyze the influence of embedded capacitors on system performance, noise reduction, and power delivery efficiency in AI/datacenter applications. We specifically investigate how embedded capacitors impact large signal phenomena, validating findings through both measurements and simulation, and present methods for effectively modeling small signal analysis with these components. We also discuss manufacturing challenges and examine the impact of lateral versus vertical power delivery systems; specifically, we address how vertical power, while more efficient and higher performance due to proximity to the chip, removes the ability to place backside decoupling. This work provides comprehensive insights into leveraging embedded capacitors to optimize PDN design for next-generation ASICs.

The Octal Small Form Factor Pluggable (OSFP) connector is a multichannel high-speed interconnect to meet the increasing data transmission demands for 5G/6G networks. However, the increasing data rate to support 800 Gb/1.6 Tb Ethernet networks presents critical signal integrity challenges. Ground resonances induce significant signal loss and crosstalk degradations, violating channel response specifications and limiting next-generation performance. This work utilizes two mitigation strategies: (1) dielectric material segment insertion for phase control and (2) anti-nodal airbridges connection of ground conductors. These methods effectively suppress energy mutual coupling between the signal propagation mode and ground resonant mode, thereby reducing resonance degradations up to 67 GHz. Integrated S-parameter metrics, including insertion loss deviation (ILD) and integrated crosstalk noise (σₓ), confirm that the degradation improvements do not compromise baseline performance. Furthermore, we correlate S-parameter degradation with eye diagram impairments. By decomposing four-level pulse-amplitude modulation (PAM4) eyes into 2-bit binary transitions (e.g., 00-01, 01-11…), we extract key figures of merit such as jitter, distortion, and settling time. Comparison between the pathfinding and the original models demonstrates how signal integrity degradations affect these eye diagram parameters. This comprehensive analysis establishes a systematic framework to quantify the impact of resonance on high-speed channel performance. Read More

Modern PCB designs and BGA packages are continually shrinking in size, which directly impacts signal integrity (SI) performance. As component dimensions decrease, maintaining strict SI requirements becomes increasingly challenging. For example, near-end crosstalk (NEXT) is highly sensitive to the physical spacing between vias and traces—meaning that as BGA and PCB layouts become more compact, crosstalk levels tend to increase In this work, we present a novel via structure that significantly improves crosstalk performance, even in extremely high-density designs. This approach offers a practical solution to the SI challenges introduced by today’s miniaturized packages and advanced PCB geometries

The paper is a continuation of the topics presented in the DesignCon 2025 paper “Practical implementation of insertion loss correction and delay characterization of test fixtures used for 200 Gb/s per lane conformance testing”. The paper will explore the limitations of a method, and provide test fixture electrical requirements, to account for the differences between the insertion loss of an actual HCB test fixture and the specified HCB reference insertion loss up to 67 GHz.

When two TDR plots don’t agree, one from a sampling scope and the other from a simulation, engineers often wonder which one to trust. This presentation explores the hidden frequency-domain factors that shape time-domain results. It explains how the quality and properties of S-parameter data, bandwidth, frequency step, causality, passivity, and reciprocity affect the fidelity of simulated TDR impedance profiles. Through visual comparisons and case examples, the session demonstrates how mismatched bandwidths can cause the Gibbs effect, how coarse frequency steps distort impedance readings, and how non-causal or non-passive data can mislead design conclusions. Participants will also learn how to select an optimal rise time based on available S-parameter bandwidth and how to validate the step edge shape used in simulations. By connecting the dots between frequency-domain integrity and time-domain clarity, this presentation helps engineers avoid common pitfalls in TDR correlation and empowers them to “see time clearly.” Whether you have access to a TDR instrument or rely solely on S-parameter measurements, this session provides actionable guidance for producing reliable impedance analysis across both domains. This presentation is designed for signal integrity engineers and hardware designers who work with S-parameters, TDR instruments, or both. New engineers will learn how S-parameter data quality and setup parameters, such as bandwidth, frequency step, and rise time, influence simulated TDR. Experienced engineers will gain a deeper understanding of how to correlate frequency-domain and time-domain analyses to ensure consistency between simulation and measurement. Attendees will leave with a practical workflow to confidently produce TDR results from measured S-parameters that align with hardware measurements within a few percent.

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Instrument and probe manufacturers have been rolling out new isolated probe products at a rapid pace. Not long ago, industry rushed to adopt the power rail probe. Has that technology lost favor? Are isolated probes truly better—or more importantly, are they necessary? In this session, we’ll explore common power integrity measurement challenges and evaluate the impact of key probe metrics. This will provide a direct, quantitative basis for probe choice and define the minimum characteristics required for each type of measurement. We’ll also examine: What has changed since the introduction of the power rail probe Why power rail probes are no longer sufficient on their own How to extend their usability in modern applications By the end, you’ll know when isolated probes are essential, what the minimum probe characteristics are, and how to use this knowledge to improve your measurement accuracy, which also leads directly to better simulation correlation.

As AI workloads drive unprecedented data center bandwidth demands, 400G per lane interconnects will become critical for scale-up and scale-out architectures. As the industry approaches these ultra-high-speed interconnects, there is growing interest in evaluating the feasibility of 400G PAM4 signaling and alternative modulation schemes such as PAM6, and PAM8 signaling. This paper explores the challenges and opportunities in enabling 400G performance over copper media, through a comprehensive analysis at interconnect and channel-level, particularly focusing on pluggable interfaces which remain central to scalable data center networking. Current form factors may limit the number of applications that copper can enable for next-generation interfaces, prompting a re-evaluation of design and possibly a transition to new form factors. We present system-level performance assessments for existing and proposed alternate 400G pluggable form factor, with a focus on end-to-end system performance for passive, retimed and active linear solutions. System modeling, simulation enhancements, and sensitivity analyses of host transmit and receive parameters are conducted to guide design optimization. Throughout, we highlight key trade-offs between modulation formats and baud rates and propose critical design considerations for high-performance active ICs in future 400G systems. Read More

As SerDes signaling speeds advance towards 200 GBps and beyond, maintaining signal integrity becomes increasingly challenging due to heightened sensitivity to loss, reflections and crosstalk. This work examines key electromagnetic factors affecting next-generation channels, beginning with the impact of the package-with-board; where rising data rates make, structural variations can lead to resonances and crosstalk. The second section introduces Eigenmode analysis to characterize cavity resonances within the combined package-with-board structure and outlines mitigation approaches for minimizing resonance-induced notches and impedance deviations. The third section investigates crosstalk arising from differential-pair orientation within the package ball map, providing a detailed comparison of square and hexagonal ball-grid configurations using power-sum and integrated crosstalk metrics across multiple data rates. The final section discusses on-package interconnect architecture as an alternative to traditional package-with-board routing when targeting bandwidths approaching 100 GHz and beyond. Collectively, this paper provided a systematic methodology for evaluating resonances, orientation-dependent coupling and on-package interconnect solution for high-speed SerDes interconnects.

Arbitrary Waveform Generators (AWGs) have become indispensable tools for high-speed I/O testing due to their ability to generate precisely controlled, repeatable signal patterns. In this work, we extend the application of AWG-assisted digitalization to physical channel modelling with fractional sampling rate, targeting 112 Gbps PAM4 signaling with a focus on Serdes Interference Tolerance (ITOL) and Jitter Tolerance Limit (JOTL) characterization. By digitally constructing worst-case PAM4 waveforms incorporating insertion loss (IL), pre-/post-cursor FFE, random noise, and jitter elements, the AWG is used to emulate physical link conditions in a highly flexible and automated manner. Our method enables programmable reproduction of complex test scenarios without reliance on extensive hardware setups. The proposed approach not only accelerates compliance testing workflows but also supports design-stage margin analysis and regression testing through consistent waveform replay. Comparative results show close alignment with traditional analog stress setups, validating the fidelity and robustness of the AWG-assisted framework in advanced signal integrity applications.

Many AI vision systems fail in production despite achieving high inspection accuracy. While accuracy is table stakes for deployment, it is rarely sufficient on its own. In connector manufacturing, long-term success depends on whether inspection systems are designed end-to-end and trusted by operators and quality teams as products, defects, and production conditions evolve. Drawing from 1000+ camera deployments in 2025 alone, this talk examines why AI inspection breaks down across the connector stack, from pins and cages to final assemblies, despite being highly accurate. We show that the most costly failures are driven by disagreements on what good quality looks like and new defect modes that never appeared in training. We define what makes an AI inspection system deployable at scale and how high accuracy is maintained as systems grow. In practice, this requires tools that: ● Capture and learn from in-production data, enabling fast retraining workflows ● Enable quality teams to standardize inspection criteria, reducing subjectivity ● Provide explainability to build trust and support rapid root-cause analysis Transfer defect knowledge from existing products to new designs so inspection starts near production-ready Attendees will leave with practical approaches to scale AI vision beyond isolated pilots into system-level inspection improvements for connector manufacturing.

Automotive radar performance at 77 GHz is highly sensitive to variations in paint-layer thickness and dielectric constant, yet physical testing on production fascias is costly and time-intensive. We propose an end-to-end, simulation-only workflow that couples high-fidelity FEKO electromagnetic (EM) simulations with a supervised machine-learning surrogate model to predict radar cross-section (RCS) across realistic paint-parameter ranges. By sweeping paint thickness (0.1–1.0 mm), dielectric constant (εᵣ 2.0–5.0), and incidence angles on a curved vehicle-panel model, we generate a comprehensive synthetic dataset of RCS signatures under typical roadway clutter. A gradient-boosted regressor is trained to interpolate intermediate parameter values, maintaining mean absolute error below 5 dBsm compared to FEKO ground truth. Once trained, the surrogate delivers RCS predictions in under 100 ms—enabling rapid “what-if” analyses of paint tolerances purely in software. This approach facilitates virtual ADAS calibration by allowing immediate adjustment of radar gain and filtering parameters based on simulated paint-layer variations. Attendees will gain a turnkey methodology for creating and deploying ML-driven EM surrogates that eliminate the need for physical prototyping while meeting automotive accuracy and reliability requirements. Read More

This work presents a fully functioning AI-driven multi-agent system designed for autonomous signal integrity analysis of interconnects. We demonstrate how high level request invokes an agent to execute top to bottom PCB sign-off flow that analyses post-layout PCIe interconnects on a printed circuit board, performing 3D extraction, compliance validation, and report generation without human intervention. Unlike traditional assistant-style AI, the system offers production-grade reliability through predictable execution and reproducible agent behaviour. The architecture is scalable, tool-agnostic, and deployable in secure local environments. We discuss agent orchestration, flow validation, memory, and communication models required for production-grade deployment. This is a practical open source blueprint for evolving from human-centric EDA to an intelligent, agentic ecosystem capable of automating complete interconnect design process in real-world scenarios.

Modern Systems-on-Chip (SoCs) often consist of multiple power domains, each requiring a carefully engineered power delivery path to meet target resistance or impedance specifications. In the PCB pre-layout stage, this task is particularly challenging, as engineers often rely on best practices or trial-and-error methods without automated guidance. These approaches may result in non-optimal solutions and long iteration cycles. To address this, a reinforcement learning-based method is proposed, where each power domain is treated as an agent that autonomously routes and synthesizes its own power shapes. Using Q-learning, agents choose optimal stackup layers, construct minimum spanning tree (MST)-based initial shapes, and iteratively grow segments across layers while avoiding overlaps. If the target resistance is unmet, a secondary agent places buried vias in centroid-aligned overlap regions between shapes. Resistance is computed dynamically using an efficient in-house contour integral method (CIM)-based solver, providing real-time feedback for learning. A shared reward encourages collaboration across agents to minimize resistance and ensure electrical connectivity. The framework has been evaluated across multiple scenarios and demonstrates consistent convergence in pre-layout stackup and power shape synthesis, offering a scalable and automated alternative to manual design practices. Read More

Exponential growth in model sizes (x410/2yrs) and compute resource (x750/2yrs) for training Large Language Models (LLMs) has led to advance in AI accelerators such GPUs, FPGAs, and ASICs. As computing hardware strives to meet AI performance demands, the “Memory Wall” has emerged as an immediate performance bottleneck in AI computing [1]. With cutting-edge packaging technologies like fine-pitch Silicon interposer and 3D-TSV stacking, HBM has bridged the performance gap in traditional on-board memory devices such as GDDR and DDR memories over the past decade. However, HBM capacity is nearing its due to the limited size of the silicon interposer. Scaling in 3D stack is also nearing its limit, likely capping at 16 dies due to challenges in handling thin dies. Furthermore, co-packaged memory systems like HBM share a short lifecycle of compute devices, significantly increasing the Total Cost of Operation (TCO) and contributing to poor AI carbon footprint. This paper introduces, for the first time, an photonic memory architecture that includes memory modules, appliances, and associated host systems, enabling a comprehensive infrastructure for hyperscalers. Photonic link operates at 56Gb/s using NRZ signaling. A total of 7.2Tb/s full duplex bandwidth is achieved with 4-WDM with 32-channel Fiber Array Unit (FAU). Read More

This work contemplates the use of EIPS to develop system level requirements that target channels requiring less than 1pS skew.  It includes a statistical study determining contributors to skew from a ...

This is a practical, fast-moving session unpacking how the Trump Administration’s revived and expanded tariff agenda will impact the full electronics value chain—from legacy/leading-edge chips and boa...

Discuss signal integrity, power integrity, EMC risk reduction, design-for-compliance approaches, simulation and measurement alignment, and mitigation strategies with peers and potential partners in th...

We will use this presentation to touch on PCIe's ever increasing data rate and the challenges that it introduces and how to mitigate them. With 128GTPS being the current standard and data rates increa...

As PCI-SIG moved to PAM4 modulation, the interconnect budget constrained requiring improved loss and noise.  This talk discusses the recipes for a robust PCIe 6.0 and 7.0 system, validating case studi...

As signaling speeds and modulation complexity increase, accurate noise measurement becomes more challenging. Standards like PCIe Gen7 and IEEE 802.3dj now require scope noise removal for precise SNDR and jitter measurements. However, conventional noise removal methods can unintentionally amplify the sampling variation of standard deviation, leading to unreliable results or even zero-value outputs. This paper introduces an adaptive scope noise removal technique that dynamically adjusts the amount of noise removed based on the measured noise and sample population. The method provides a practical and statistically grounded way to balance measurement bias and variation. Simulation results and real-world examples demonstrate how this approach significantly reduces variation while maintaining accuracy, making it ideal for high-speed signal validation and compliance testing.

The AI revolution is putting enormous pressure on energy efficiency and as number of cores and connection bandwidth increases exponentially, serial links are becoming the #1 energy expenditure. It is ...

The emerging of large language models (LLMs) has posed significant challenges to the thermal management of data center. Intense GPU computation for LLMs results in localized hotspots, moreover, spikin...

Distributed capacitors play a crucial role in ensuring power integrity in modern GPUs, which demand high current delivery and minimal voltage ripple at ever-increasing switching speeds. As GPUs become...

This paper addresses the challenges of high signal loss and insufficient line precision in PCBs under Ultra High Density Interconnect (UHDI) processing. We propose a comprehensive technical solution i...

AIPC (AI Personal Computer) is reshaping the computing experience by enabling localized AI capabilities, offering breakthroughs in privacy protection, responsiveness, personalized services, and produc...

This session will cover Amphenol's industry-leading 448G interconnect ecosystem, including co-packaged copper, nearchip, backplane, front panel and cable solutions. In addition, topics such as PCIe, p...

The adoption of 106/112 Gb linear optical interfaces—commonly referred to as LPO (Linear Pluggable Optics)—is rapidly growing in data center and AI/ML applications due to their reduced power and laten...

On the path towards 448Gbps era, the bandwidth that passive channels can achieve is critical. While not limiting to specific connector form factors, this paper focuses on investigating connector via a...

In AI/ML scale-up/scale-out networks, 224Gbps SerDes is already being put into practical use. Discussions on 448Gbps SerDes as the next generation are also recognized as highly feasible, and discussio...

This session presents a hands-on exploration of advanced MEMS switch technologies for high-speed digital and mmWave applications, featuring both demonstrations and technical discussion. We will presen...

The shift to 448Gb/s Ethernet for AI-driven workloads demands optimized interconnect choices between copper and optical solutions to meet stringent bandwidth, reach, latency, power, and cost targets. ...

Paid all-access passholders, event committee members, media, and speakers can fuel up between sessions with this complimentary networking lunch.

Computationally Efficient, design and optimization of UCIe-Based Chiplet Interconnects with Hatched Ground Plane

Press-fit connectors remain valuable for their mechanical robustness and compatibility with established PCB manufacturing processes, while compression-based solutions enabled by advanced fabrication t...

As Ethernet speeds advance to 200Gbps and soon 400Gbps, the associated fundamental frequencies reach 50GHz and 100GHz, respectively. At these frequencies, signal integrity (SI) requirements become increasingly challenging. Currently, the CK specification does not define TX-to-TX crosstalk, which may present a significant oversight as data rates continue to increase. At higher speeds, the impact of TX-to-TX crosstalk can no longer be neglected. In this work, we investigate and characterize the conditions under which TX-to-TX crosstalk becomes critical. Our findings indicate that this parameter will likely need to be addressed in future specification updates, such as in the upcoming 802.3dj generation and beyond.

Achieving a 448 Gb/s serial link presents significant challenges in terms of bandwidth and signal integrity. While advanced modulation schemes such as PAM-6 and PAM-8 can help reduce the required bandwidth, they introduce trade-offs in noise tolerance and system complexity. These challenges are further amplified in next-generation data center architectures, where large package sizes and multi-layer core stackups exacerbate channel loss and impose mechanical constraints due to BGA size limitations and warpage concerns. Additionally, the escape routing between the BGA and PCB must be carefully optimized to preserve channel performance at such high data rates. In this work, we demonstrate the feasibility of a full end-to-end 448 Gb/s PAM-6 serial link implementation with different package interconnect schemes including BGA and co-packaged copper (CPC). Our design includes a high-performance package channel featuring a multi-layer-core (MLC) stackup, optimized BGA transitions and a carefully engineered PCB escape structure, and CPC. The proposed interconnect solutions provide a viable path forward for future datacenter and AI designs targeting ultra-high-speed interconnects in advanced data center systems. Read More

The constant demand for higher bandwidth, now further fueled by the rise of AI, is pushing the SerDes community to continue to double the speed from generation to generation. This time however, while going for 448Gbps, there seems to be a number of “brickwalls” in the path. Channel/media presents signal integrity challenges much more severe than ever before. Package and connector technologies show significant limitations when targeting Nyquist frequencies near and above 100GHz. On the silicon side, in addition to meeting the bandwidth requirement, achieving adequate jitter downscaling is also challenging at frequencies above 100GHz. A number of analyses across the industry have shown that PAM4 with Nyquist frequency placed @112GHz may not serve this time. Instead, some other modulations such as PAM6, PAM8, DMT, and FBMC are now being considered as potential replacements. While many of the previous analysis have primarily focused on channel/media feasibility study, this paper focuses on an in-depth relative comparison between PAM6 and PAM8 modulation schemes from a SerDes perspective and summarizes several aspects and implications of employing these schemes on SerDes blocks. Toward this goal, a series of tests are performed to generate, acquire, and process data to perform the comparative analysis and impact of major SerDes block functions on the overall performance. Read More

At data rates targeting 224 Gbps and beyond, conventional conductor loss models fall short in explaining the insertion loss and phase delay variations observed with different copper foil surface treat...

The maximum data rate of high-speed interfaces has increased dramatically in response to the explosive demand from data centers and high-performance computing, with serial interfaces reaching 112 Gbps...

The transition to high-speed, high-density cable harnesses for network equipment, such as a project with 2048 pairs, demands robust signal integrity (SI) testing to ensure performance at 51.2T switch ...

Discuss AI applications, machine learning workflows, model validation, data readiness, and practical deployment considerations with peers and potential partners in this open-to-all networking session....

Fuelled by AI workloads, next generation scale-up and scale-out networks put tremendous strain on the design of high-speed interconnect solutions. Data rate growth to 448Gb/s is key, though by far not...

The demands of advanced Die-to-Die IP links driven by AI requirements are pushing the capabilities of IBIS-AMI modelling.   Once solely focused on chip-to-chip SerDes interconnect, IBIS-AMI has succes...

Modern AI and datacenter systems, equipped with complex multi-domain Power Distribution Networks (PDNs), grapple with substantial challenges stemming from large-signal crosstalk and ground bounce. The...

The S-parameter measurements displayed on the front of a VNA are only part of the information contained in the S-parameters. Often, we want to data-mine the information contained in S-parameters using...

In high-speed IO links, transmitter equalizers, like pre-/de-emphasis, are indispensable for high-frequency loss compensation. However, such schematics requires complicated control circuits with high ...

The EU introduced the Cyber Resilience Act, a new regulation that mandates digital product vendors to bring more secure products to market. Vendors must keep their products secure by consistently patc...

The accuracy of Transmitter (Tx) Equalization Preset measurement in PCIe applications is of paramount importance. When Tx Presets deviate too far from the target Presets, it could affect link performance and interoperability. It is for this reason that the measurement tolerance for Tx Preset parameters such as Preshoot2, Preshoot1, and Deemphasis in PCIe 6.0 Electrical Specification were reduced from +/- 1 dB for 32 GT/s NRZ Signaling to +/- 0.5 dB for 64 GT/s PAM4 signaling for nearly all Preset parameters and the same window limits are carried over to PCIe 7.0 Electrical Specification. The accuracy of the measurement is impacted by several parameters, such as oscilloscope choice, channel loss in the measurement setup and the measurement method. Several different Preset measurement methods have been used across previous PCIe generations. The focus of this paper is to demonstrate, with comprehensive sets of measured data, that Linear Fit Pulse Response (LFPR) method results in the most robust measurements across oscilloscopes, lab conditions, and channel loss variations for both 64 GT/s (PCIe 6.0) and 128 GT/s (PCIe 7.0). Read More

Modern power distribution networks (PDNs) in high-performance systems face increasing complexity, especially when supporting multiple loads across shared supply rails. Traditional target impedance methods, while foundational, often fall short in capturing the spatial and frequency-dependent behavior of these systems. This work introduces a novel approach that combines Cumulative Power-rail Noise (CPN) and the Reverse Pulse Technique (RPT) to bridge the analytical gap between time-domain performance metrics and spatially distributed frequency-domain data. The result is a deeper understanding of how spatial filtering, decoupling placement, and layout decisions affect both local and system-wide power integrity.

Power Distribution Network (PDN) and power supply testing face increasing complexity as modern Voltage Regulator Modules (VRMs) and voltage regulators increasingly employ non-linear control loops. Thi...

Accurate terminations are essential for accurate high-speed signal integrity (SI) measurements. Traditional approaches using SMA connectors or soldered resistors can be cumbersome, costly, and impractical—especially for dense PCBs and during early-stage evaluation, where iterative layout changes are common and time-consuming. This study investigates an alternative method using absorber materials as temporary terminations, applied directly to PCB landing pads without requiring permanent hardware. We evaluate several magnetically and electrically loaded absorber materials on two types of test structures: standard SMA pad layouts and ball grid array (BGA) footprint pads on a Signal Integrity Test Vehicle (SITV) board. S-parameter and time-domain reflectometry (TDR) measurements were used to compare their performance against conventional 50-ohm terminations. Our results show that electrically loaded absorbers, when applied with appropriate and consistent pressure, can closely match the impedance and reflection behavior of high-quality terminations. Notably, on BGA pads, some absorbers maintained low reflection (below −10 dB) and impedance near 50 ohms over a wide bandwidth. This technique offers a fast, non-invasive, and cost-effective method to evaluate SI performance directly on existing layouts, even in complex or connector-limited areas. It is particularly useful for early validation, debugging, or test scenarios where modifying the board is undesirable. Read More

The shift to PAM4-based signaling schemes has introduced more complex figures of merit for transmitter characterization, such as signal-to-noise-and-distortion-ratio (SNDR). However, higher-order modulation also means increased impact of signal impairments not only on receiver operating margins but also on the robustness of methodologies used by test equipment to characterize devices. Channel loss can be a particular challenge – where a real-world receiver typically leverages adaptive equalization to minimize BER/SER, the same luxury is often not available within a test environment. For example, SNDR measurements are typically required by the relevant test specification to be made at a particular equalization setting that may be non-ideal for the channel in question. In another case, transmitter FFE coefficients are measured relative to a reference “no emphasis” waveform, making adaptive channel compensation unsuitable. At longer, higher-loss channels, conventional clock-data recovery emulation methods struggle to function correctly and become a significant impediment to these measurements. This paper will examine why this is, and show its practical effects using real-world SNDR and Tx FFE measurements. These results will be compared and contrasted to those achieved using a novel, highly loss-tolerant clock-data recovery methodology which enables measurement on highly lossy channels. Read More

Optimizing signal integrity performance in the interconnect components is essential to enable PCIe running at 128Gbps and beyond. Conventional PCIe topologies route signals through the package, BGA/socket, and then motherboard which can be cabled out to an end point device. Pin field area remains to be a major source of reflections and crosstalk due to routing area congestion and thick PCB board adopted in AI and MCP designs. This work proposes a novel top side interposer architecture, where a high-speed cable, through a near package connector (NPC), egresses directly from the interposer to the end point device, thus PCIe high-speed signals completely bypassing the BGA/socket and pin field area. Experimental results of this proof of concept demonstrate that this approach substantially reduces crosstalk and reflections, enabling robust PCIe 7.0 operation at 128Gbps and providing a scalable solution for future PCIe generations.

A novel method utilizing airline measurements is introduced to accurately and efficiently determine the dielectric constant and loss tangent of a material for broadband applications. This approach surpasses traditional methods like NRW/NIST in precision and efficiency. The process involves measuring two airlines of different lengths, both with and without the material under test (MUT), which are shaped as hollow cylinders matching the airline lengths. Ensuring the insertion loss of fixture A is similar to fixture B is crucial due to the different genders on the airline ends. The Automatic Fixture Removal (AFR) process is then applied to both scenarios to obtain precise S-parameters of two short coax lines, effectively eliminating imperfections at the airline ends. By utilizing the closed formula for multilayer lossy coax lines, the physical lengths and metal loss are negated, allowing for the accurate calculation of the dielectric constant and loss tangent of the DUT. This method is independent of metal loss and physical lengths, thus eliminating errors from measurement uncertainties. Since there are no discontinuities at the reference planes,  the resonance issues inherent in the NRW/NIST method are completely avoided.          The proposed method has been validated through simulations and comparisons with commercial resonator methods( Swissto 12 material characterization kit). Read More

Attackers are increasingly bypassing OSlevel defenses by exploiting weaknesses far below the software stack—compromising BMC firmware, manipulating SPI flash, abusing debug interfaces, and targeting o...

In modern data communications and AI architectures, signaling speed and density limits are being pushed to their physical boundaries. To achieve speeds of 224-448 Gbps, high-speed twinaxial cables are...

In this paper, we propose an extended scale cache (ESC) stacked-GPU–HBM architecture, where the last-level L2 cache is extended onto a dedicated ESC die stacked above the GPU to reduce HBM accesses ov...

Abstract: Advanced SoC IC Packaging Technologies (Panel session) This panel will explore the latest advancements in heterogeneous integration and advanced SoC IC packaging technologies, with a focus on 2.5D, 3D, and emerging 3.5D architectures. Drawing from the experiences of leading technology providers across the industry, the discussion will center on monolithic and chiplet-based heterogeneous packages designed for server-class, AI, and data center applications. The session will cover: 1. Package architectures ranging in size from 45mm × 45mm to 85mm × 85mm. 2. Full stack integration including active silicon (logic or HBM dies), interposers (e.g., CoWoS, EMIB), substrate technologies, RDL (Redistribution Layers), power delivery networks, and ball grid arrays. 3. Comparative analysis of packaging methods from a performance-per-watt, manufacturability, cost-efficiency, and thermal/mechanical reliability perspective. 4. Integration of high-bandwidth memory (HBM3, HBM3E, HBM4) and implications for signal integrity, power integrity, and thermal management. 5. Trade-offs between interposer-based designs (e.g., silicon and organic interposers) versus bridged and FOWLP (Fan-Out Wafer-Level Packaging) approaches 6. Design enablement and EDA toolchain support for advanced packaging including thermal-electrical co-design, parasitic extraction, and multi-die simulation The panel will conclude by identifying the best practices and practical solutions for implementing next-generation IC packages using commercially available EDA tools and advanced manufacturing ecosystems. Read More

The rapid evolution of artificial intelligence (AI) is driving larger and highly interconnected clusters with the need to shuffle huge quantities of data between compute elements. The rapid evolution of artificial intelligence (AI) is driving larger and highly interconnected clusters with the need to shuffle huge quantities of data between compute elements. The next generation of AI compute clusters will require a variety of different communication links, each satisfying a unique set of requirements.    The OIF is studying new electrical and optical interfaces in a variety of architectures including lower power retiming architectures such as linear and Tx retimed chip-to-optical engine interfaces that meet the hyperscalers’ requirements.  These innovations for energy efficient connectivity for AI compute clusters can help bring optics into the scale-up domain for the first time.  Join our OIF industry experts to learn about these new energy efficient links, their requirements, the various tradeoffs, and the latest on the OIF's progress on Energy Efficient Interfaces for AI compute. Read More

Stay for the hosted reception following these stimulating presentations to network with the speakers and other attendees. Complimentary drinks and appetizers will be served. There is no charge to atte...

LPCAMM2, the recently adopted DRAM module standard, is gaining popularity in notebook PCs due to its compact size, upgradeability, and serviceability. However, its high-speed operation such as LPDDR5X...

Today's IC packaging solutions are increasingly complex, presenting challenges in moving to next-generation silicon nodes and integrating high-density memories for AI applications. System-level design...

As ASIC currents exceed 1000A, traditional horizontal power distribution faces challenges like DC IR drop, power delivery network (PDN) impedance, and electrothermal issues, leading to growing complex...

Bridging the gap between simulation and measurement has been a challenge in high-speed digital, especially for memory applications like DDR5. When certain test cases fail in measurement but not in sim...

Improvements in signal processing methods are required to meet the challenges of 448 Gbps Serdes links.  We present PAMXmY as a modulation strategy that can be used to greatly improve link capacity for high insertion loss channels.  PAMXmY utilizes additional DSP processing steps while maintaining backwards compatibility to previous generations of Serdes systems. The X term defines the number of signal levels used to represent the information while the Y term represents the actual number of levels transmitted.  The extra levels provide parity information that can be used by a soft forward error correction (FEC) decoder located within the PHY.  PAM6m8 is presented as an alternative to PAM6 and PAM8m16 as a possible alternative to PAM8. A family of convolutional codes are presented, and we describe the additional processing steps required to support other soft FEC engines. As well, we describe several decoding styles that trade-off correction performance and complexity. The performance of the new modulation and coding formats are evaluated against traditional receiver performance in terms of coding gain and inter-operation with the KP-FEC.  Overall, we find that PAMXmY modulation can provide 3dB or more coding gain relative to standard PAM6 or PAM8 modulation. Read More

AI increases and accelerates the bandwidth needs for its scale-up and scale-out networks, at an unprecedented pace, from 112 Gbps, to 224 Gbps, and soon, to 448 Gbps. This presentation will discuss ho...

For advanced high-speed digital and high-frequency technologies, the contribution of conductor losses become more and more important. Copper foils are often characterized by their surface roughness, a...

New applications such as artificial intelligence, autonomous cars, high performance computing, and embeded vision are driving stricter requirements for memory performance and power efficiency. These d...

This paper introduces an advanced SoC/IC packaging architecture framework based on a Tri-Loop model and a gated G0-G5 design flow that links multi-physics, governance, and manufacturing outcomes. The ...

Many AI rack architectures leverage passive cable backplanes to create scale-up network fabric, linking together GPUs/XPUs with fabric switches. AI architectures are evolving to increase the number of accelerators in the scale-up domain, increasing the quantity and physical length of the connections. At the same time, the protocol landscape with PCIe, Ethernet, and UALink is targeting higher frequencies. These trends make it challenging for passive cable backplanes to support next-gen architectures. This presentation will cover how implementing signal conditioning devices in the cable backplane cartridges solves many of these challenges. This session will dive into the trends and challenges of passive cable backplane architecture and cover the implementation details of an active cable backplane solution. Tradeoffs for mechanical, thermal, and signal integrity will be discussed.

The emergence of advanced semiconductor design paradigms such as 3D integrated circuits (3DIC) has significantly enhanced chip functionality, while simultaneously introducing new challenges—particularly in thermal management. In 3DIC, multiple dies are vertically stacked within a single package, leading to increased power density and more complex heat dissipation requirements. To ensure thermal reliability, accurate thermal simulation is essential during early design stages. Traditional methods such as the Finite Element Method (FEM) and Computational Fluid Dynamics (CFD) offer high accuracy but often suffer from high computational costs and long runtimes, especially in transient thermal analysis. To address this, acceleration techniques have been explored to improve simulation efficiency. Recent machine learning (ML)-based thermal solvers have demonstrated substantial speedups; however, most are limited to assuming uniform heat transfer coefficients (HTC) at the boundaries, which is unrealistic for practical scenarios. In this work, we propose a novel ML-based transient thermal solver that accepts spatially distributed HTC values and arbitrary power pattern sequence as input. Our solver achieves over 100× speedup compared to FEM while maintaining high accuracy, enabling efficient and realistic thermal simulation for 3DIC. Read More

For reliable receiver testing in high-speed serial links like PCIe, where loopback is used to determine the Bit Error Rate (BER), it is crucial to optimize the backchannel, the path from the transmitter Device Under Test (Tx DUT) to the Error Detector (ED). This ensures accurate signal conveyance for comparison against test patterns and precise BER evaluation of the Rx DUT. This paper presents a comprehensive approach for PCIe backchannel optimization, focusing on FFE and sampling setup tuning, while also exploring Machine Learning (ML) as a tool to predict optimized FFE and re-driver settings. We propose an efficient FFE optimization method based on pulse response, providing very good starting points for tuning the FFE taps and reducing the need for BER-based tuning. Additionally, an ED sampling setup optimization framework using Newton-Raphson search and spline interpolation reduces measurement effort while maintaining accuracy. We further explore ML models trained on lookup tables that relate channel loss to optimal FFE and re-driver settings, offering fast, predictive tuning. This method can be extended to sampling setup optimization as future work. The proposed techniques are validated for PCIe 5.0 and 6.0 systems, with potential applications to PCIe 7.0 and other high-speed serial interfaces. Read More

The need to characterize a broadband differential switch for high-speed digital performance has uncovered many challenges in the testing and measurement of such devices. Along with general RF test har...

As high-speed interconnect technologies continue to scale for data center and AI applications, accurate and repeatable signal integrity characterization is increasingly critical. This presentation int...

Optimizing the interconnect components electrical performance is essential to enable PCIe 7.0 operation at 128Gbps. Pin field area has been identified as a key bottleneck due to elevated reflections a...

As Large Language Models (LLM) evolve and become integrated across various networks, there is a growing demand for more advanced AI training and inference hardware to support their capabilities. The c...

Crosstalk is one of the dominant sources of interference in high-speed memory systems, especially for parallel interfaces, such as memory and chiplet. Statistical eye analysis commonly neglects transm...

In high-speed SerDes design, IBIS-AMI is widely used for serial link simulations, but most solutions rely on static models. These static solutions incorporate only fixed channel s-parameters and a sin...

This paper outlines a multi-agentic AI approach to complete high-speed SI/PI design, from concept to final design execution, where multiple AI agents will perform dedicated design tasks. A Q&A agent ingests domain knowledge from design documents, an optimization agent searches for optimal design solutions within the target range, and an EDA API agent will be used to interact with SI/PI tools to complete the design flow. We use a DDR5 design as an example, where the first agent obtains design parameters from product design guides, PCB stack-ups, and DFM documents and stores them in a shared memory. The optimization agent then searches for the optimal routing geometry solution, considering multiple optimization objectives and utilizing parameters stored in the shared memory. The optimization utilizes humans in the loop to ensure successful execution. The EDA agent will turn the optimized results into design constraints for the PCB router and finish the design. Such an AI-driven agentic flow serves as a co-pilot to assist engineers with these design tasks. Our key innovation centers on enabling a multi-agent flow to perform optimization reasoning rather than merely executing mundane simulation and reporting tasks. Read More

In recent years, Silicon Photonics (SiPho) high-speed interconnects have emerged as a pivotal technology for meeting increasing bandwidth and efficiency requirements in data communication systems. Whi...

AI/DC is really pushing the limits of electrical interfaces, high speed connectors and PCBs. The co-existance of Optical and electrical is not making life simpler for engineers developing next generat...

Co-Packaged Copper (CPC) is an emerging interconnect architecture designed to meet the signal integrity, power, and density challenges of next-generation Ethernet systems operating at 224Gbps-PAM4. In...

This paper presents a novel method of fitting the optical channel to an IBIS-AMI Redrive model. The method aims to address the challenges in evaluating the opt-electronic performance of  Linear-drive ...

In modern digital circuit design power integrity analysis, timing analysis combined with power supply noise effectively account for Power Supply Induced Jitter (PSIJ), helping to prevent over-design. ...

The rapid pace of development in AI-related signal integrity presents both opportunities and challenges. In this environment, maintaining solid correlation between simulation and measurement—an essent...

The rapid growth of AI/ML market has driven demand for advanced packaging technologies, including silicon interposers and bridges used in chiplets, 3DHI, and 3DIC architectures. These structures would...

No description available.

High-performance systems—AI, data center, and HPC—demand ever tighter regulation of power rails. As VRM topologies evolve and new capacitor technologies emerge, validation methods must also improve. S...

This work presents a targeted EMI-mitigation approach that combines microwave holography with custom 3D-printed absorbers to suppress radiated emissions in high-speed optical systems. Microwave holography is used to isolate the true radiating structures by reconstructing the propagating field components responsible for far-field emission. The localized radiation hotspots identified by holography guide the design and placement of compact absorber structures fabricated from carbon-loaded PLA. Two absorber styles are evaluated: an internal block absorber for PCB-level radiation sources, and a frame-style absorber for suppressing leakage through optical cage and front-panel gaps. Measurements using a QSFP module compliance board show that these printed absorbers reduce radiated emissions by 6–12 dB across the 25–27.5 GHz band. The workflow (source localization, absorber design, rapid fabrication, and validation) requires no PCB or enclosure modifications, potentially providing a fast, low-cost, and highly effective mitigation option for late-stage EMI debugging in tightly packaged high-speed systems. Read More

AI/ML techniques are increasingly being used to optimize high-speed link design, particularly in SerDes for PCIe, USB, and memory interfaces. These systems are complex and involve multi-dimensional design tradeoffs, making them ideal for machine learning–driven exploration and tuning. The research primarliy focuses on following areas: Equalizer and Filter Tuning SerDes Parameter Sweeps & Channel Optimization Adaptive Clock and Data Recovery Loop Tuning Bit Error Rate (BER) Prediction Channel Modeling & S-parameter Emulation Jitter and Noise Classification

AI/ML is driving data center network bandwidth to 100s of Petabits/s and individual switch bandwidth to 100+ Tb/s. Achieving this scale requires integrating massive numbers of high-speed SerDes—either 1024 lanes at 100 Gb/s or 512 lanes at 200 Gb/s for 100T-class switches. Looking ahead, 200T switches require 1024 SerDes at 200 Gb/s or 512 lanes at 400 Gb/s.  Traditional switch designs using BGA packages face mounting challenges at these speeds and densities. Signal integrity degradation, power inefficiencies, and mechanical limitations such as substrate warpage and BGA reliability are critical bottlenecks.  Higher insertion loss in the substrate and PCB leaves very little loss that can be allocated for rack-scale interconnects. Switch designs based on co-packaged connectors (CPC) enables passive copper channels from the switch to rack, bypassing the SI and power limitations of BGA-PCB designs.  At 200 Gb/s, CPC offers significantly improved SI compared to BGA and NPC alternatives, enabling longer cables. At 400 Gb/s, traditional approaches may no longer be viable, and CPC along with CPO become essential technologies.  However, CPC introduces new challenges in packaging assembly, mechanical design, thermal management, testing, and reliability.  This paper explores the benefits and the challenges of CPC based solutions for high radix switch systems. Read More

As data rates continue to scale beyond 224Gbps, the corresponding Nyquist frequencies are pushing the limits of current high-speed interconnect and cable assembly characterization. While standard test...

Traditional approaches to high-speed connector breakout design rely on full-wave solvers like HFSS or CST, which are accurate but computationally intensive and require careful setup. Our objective is to accelerate early-stage design analysis while maintaining high accuracy using machine learning (ML). We present an ML based tool that instantly predicts key signal integrity (SI) metrics such as Return Loss (RL) and Time-Domain Reflectometry (TDR) for high-speed connector breakout regions. It uses percentile-based sampling from HFSS simulations and features an intuitive graphical interface. The tool accepts a wide range of design inputs, including dielectric constant (Dk), antipad diameter, stub length, and via dimensions. Engineers can input design variables and instantly view predicted RL and TDR responses with confidence levels. The tool supports rapid "what-if" analysis and prescriptive analysis, enabling efficient exploration of multiple design alternatives. This approach reduces reliance on repeated full-wave simulations and enables informed decision-making much earlier in the design cycle. Future updates aim to support automatic HFSS compatible model generation, further streamlining the validation workflow. Read More

PCI Express 7.0 has arrived! Served as high-bandwidth, low-latency, and keep track of the aggressive tradition of doubling I/O bandwidth every three years. PCI Express technology has continued to be a...

Each successive generation of AI and accelerator-based systems continues to drive substantially higher bandwidth and data rate requirements across the ecosystem, increasing the need for robust SI/PI m...

Zero Bias TLVR is a proposed modification of the standard TLVR topology designed to better utilize the TLVR magnetic structure. To achieve the higher efficiency, the selection of inductors and the PCB...

AI/ML has driven the evolution of data center equipment speed from 200G to 400G, increasing channel bandwidth up to 90GHz. BGA soldering is the main way of chip and PCB assembly, delivering high-speed...

This paper focuses on multi-die packages utilizing multiple chiplets, whereby optimizing next-generation die-to-die (D2D) interconnects by addressing two critical signal integrity parameters: Insertio...

Paid all-access passholders, event committee members, media, and speakers can fuel up between sessions with this complimentary networking lunch.

Hardware startups face a unique scaling challenge—moving fast without breaking quality, compliance, or cash flow. In this panel, CEOs from contract manufacturing and precision machining join leaders i...

As high-speed interface standards continue to evolve, JESD204C has emerged as a critical serial link for connecting ADCs, DACs, FPGAs, ASICs, and chiplet-based architectures. Achieving reliable JESD20...

Connect with fellow emerging engineers and rising leaders in an open networking session designed for meaningful, peer-to-peer conversation. This fast-paced format creates multiple short interactions w...

The bandwidth required for XPU interconnection is staggering. With limited XPU 'beachfront' area, maximizing density (Gbps/mm) through higher individual lane speeds is critical. Simultaneously, the ma...

Design-in for 224 Gbps architectures has begun, due largely to the intensive data needs of AI HW architectures. What have we learned so far about signal integrity, system architectures, materials science, processing techniques, and test& measurement challenges?  This expert discussion will examine how we can design, build, and test 224 Gbps systems and achieve acceptable SI in light of technological and physical limitations.

The rise of AI and high-performance computing (HPC) is pushing the limits of power delivery design. As xPUs grow in complexity, power density, and I/O bandwidth, maintaining power integrity across system-level platforms becomes increasingly difficult. Traditional power delivery networks (PDNs), which rely heavily on ceramic decoupling capacitors are now reaching fundamental limitations. Chief among these is parasitic inductance, particularly equivalent series inductance (ESL), which leads to impedance peaking at mid-frequencies and degrades overall system performance. This paper introduces silicon capacitors as a breakthrough solution to these power integrity challenges. Offering almost ideal ESL, ultra-thin profiles, and flexible integration into package substrates, silicon capacitors significantly flatten PDN impedance and suppress mid-frequency noise that conventional approaches fail to address. These devices enable proximity decoupling directly at the point of load, improving transient response and unlocking performance in dense chiplet-based architectures. System-level PDN models, impedance vs. frequency comparisons, and cross-sectional package diagrams will be presented, to illustrate capacitor placement strategies. Application-specific examples—including real product imagery—will demonstrate the practical benefits of silicon capacitors in designs. The configurability of silicon capacitors in terms of thickness, termination types, and form factors will also be discussed to support implementation across varied packaging platforms. Read More

Next-generation AI scale-out applications are driving the requirement for 200G per lane optical interconnects to meet AI cluster bandwidth needs.  As optics data rates increase, the power consumption ...

In most existing models, only the roughness of the electrolyte side (matte side) of copper foil is considered to estimate conductor loss. However, during PCB manufacturing, a chemical treatment often ...

The evolution toward 448 Gb/s wireline serial links presents substantial challenges in analog front-end design, primarily due to extreme analog bandwidth demands. PAM4 modulation at 112 Gbaud—used in ...

As DRAM interface speed continues to increase, precise jitter decomposition becomes indispensable for validating timing margin and high-speed performance. This paper presents a new heuristic jitter de...

This session will cover the latest test methods for High Speed Serial Serdes Tx, Rx, and Return Loss Compliance and Validation. Examples will include standards such as USB4/Thunderbolt, DisplayPort...

Join us for the IEEE EMC Society presented Women in Engineering (WIE) sessions and reception at the 31st anniversary of DesignCon. Tom Braxton, EMC Society President, 2026-2027, will provide the offic...

High-speed, ultra-large-scale switching and computing products increasingly rely on cable solutions due to their significant advantages over backplane solutions, offering compact and high-density conn...

In this work, a machine learning (ML) based method for fast full impedance profile prediction including self and transfer impedances of power delivery network (PDN)-ports is proposed. The method enables the generation of complete impedance matrices for printed circuit boards (PCBs) within milliseconds. Substituting costly full-wave simulations in the PDN design for PCBs with fast ML based predictions can significantly accelerate the design process. The utilization of autoencoders in the neural network architecture provides an efficient mapping of the data to a latent space, with high information density. A combination of the autoencoder with a feed-forward neural network (FNN) is trained on self and transfer impedances respectively. The autoencoder architecture utilizes latent space representations to capture electromagnetic (EM) similarities across PCB designs, enabling both impedance prediction and design comparison. By evaluating design similarity in latent space, the proposed method facilitates the reuse of prior decoupling strategies, streamlining the PDN design workflow. The PCBs in the investigation feature different shapes, with up to 14 metal layers and more than 25 power vias. Furthermore, the application of the proposed method for more realistic modern high-speed PCBs is investigated. The training dataset is generated using a physics-based simulation tool and can be found on the SI/PI-Database from the Hamburg University of Technology (https://www.tet.tuhh.de/en/si-pi-database).   Read More

As high-speed digital systems scale to tens of gigahertz, maintaining both power integrity (PI) and signal integrity (SI) becomes increasingly challenging due to reduced supply voltages and faster switching speeds. PI ensures stable power delivery, while SI minimizes bit errors—yet their interdependence is critical in deep sub-micron technologies, where power ripple can directly degrade signal quality. This paper presents an AI-driven, software-based methodology to emulate power supply ripple through high-speed serial (HSS) jitter analysis. By leveraging Time Interval Error (TIE) spectra, the approach isolates jitter sources and enables ripple estimation from reconstructed data/clock signals—without requiring immediate hardware changes. Crucially, it introduces machine learning models to intelligently map the spectral characteristics of power supply noise and HSS jitter, enabling deeper insight into cross-rail interference and PI-SI interactions. Engineers can apply this method to identify dominant jitter contributors, correlate ripple with signal degradation, and optimize decoupling strategies early in the design cycle—enhancing system robustness and reducing costly iterations.  Read More

PCIe 7.0 introduces data rates of 128 GT/s, requiring tighter crosstalk control on all link components. Connectors must meet specifications up to 48 GHz and maintain backward compatibility. Channel margins can vary considerably from design to design, depending on factors such as minor excursions and overall crosstalk levels. This study explored the impact of crosstalk on channel margins in a two-connector topology, showing that specific frequency excursions have a greater effect than increasing broadband crosstalk. A novel technique was developed to artificially induce crosstalk in the connectors by manipulating the S-parameters. This enabled the simulation of various levels and peaks of crosstalk across the entire spectrum. The results of the channel analysis provided quantified metrics of crosstalk sensitivity and optimization predictions, in which far-end crosstalk was identified as a major contributing factor. The study offers insights into frequency-dependent crosstalk behaviors critical for designing and selecting PCIe 7.0 connectors. It contributes to the development of the PCIe 7.0 ecosystem by providing valuable information on crosstalk management and component selection for improved channel optimization, ultimately supporting the continued evolution of PCIe technology. Read More

Constant demand for higher bandwidth in data connectivity continues to push SerDes developers to double data rate every generation. Datacom industry, at the verge of entering 400+Gb/s speeds, is now facing ever more challenges than before. Fulfilment of Signal integrity, among other things, is at the mercy of achieving improvements in channel characteristics from bandwidth and crosstalk aspects. Toward this end, more radical signaling schemes that could relax channel requirements are receiving more attention yet again. So far, single-ended (SE) signaling has been avoided due its known concerns around noise immunity. But this has come with a rather large two fold penalty in bandwidth efficiency. Even if noise immunity of SE signaling is addressed or accepted, the fact that channel design and development are highly optimized for differential signaling could present yet another obstacle for SE signaling. From this aspect, the idea of applying Multi-In Multi-Out (MIMO) processing technique to SE signals travelling through differential channels could provide a possible solution. This paper is an attempt to study the feasibility of SE MIMO signaling so that the next generation 400+Gb/s rate target can be achieved by doubling the bandwidth efficiency rather than speed. Read More

Electronic design automation (EDA) has advanced significantly, enabling co-design and co-simulation of complex electronic (sub)systems - including multi-die, assembly and package - through integrated ...

With high-speed on-board electrical communication links operating at frequencies above 50 GHz, analysis of plated-through-hole (PTH) via performance requires modeling the via as a three-dimensional tr...